Most digital systems have at least one asynchronous input. For example, a computer can have a power-on reset signal, an interrupt signal or a data signal being input at a frequency independent of the system clock. All such systems must synchronize the asynchronous input signal to the system clock before utilizing the input signal.
One method of synchronizing the input signal to a system clock is to use a bi-stable latch or storage element. A flip-flop is one such bi-stable storage element. A conventional flip-flop requires that an input signal, usually a data signal, have a minimal setup time. Setup time is the amount of time the input signal must be stable before the system clock transitions to store the input signal in the flip-flop. The input signal must also remain for a minimal hold time, which is the required time for the output signal of the flip-flop to change state to the value of the input signal.
However, since the input signal is asynchronous to the system clock, an event may occur where either the setup or hold time will be violated. This event causes the output signal of the flip-flop to be an unknown state. Further, the final transition of the flip-flop's output signal may be abnormally delayed. This phenomenon, known as "metastability," can cause errors in other circuits that are coupled to receive the synchronized input signal.
Metastability occurs at a certain time window of the system clock transition. Referring to FIG. 1, the graph shows a flip-flop propagation delay versus a data input timing. The left side of the graph, defined by line 10, shows the input data signal transition occurring well in advance of the setup time and clock transition. This condition causes an output 12 of a flip-flop to become stable after a normal propagation delay T.sub.p, as illustrated in FIG. 1.
Metastability occurs in a time window T.sub.w. During time window T.sub.w, the input data signal transitions within a certain time before or after the transition of the system clock. As a result, output signal 12 is delayed for a time T.sub.pde. If the input signal violates the hold time, output 12 may not follow the input signal, as shown at 14. For a further discussion, please refer to Hoang Nguyen, How to Detect Metastability Problems, ASIC & EDA, February 1993, which is incorporated herein by reference.
As designers push circuit frequencies to 200 MHz, one area of concern is how metastability will affect system reliability. The increasing frequencies have an adverse effect on the mean time between failures (MTBF) due to synchronization failures caused by flip-flop metastability. The MTBF increases exponentially with the clock and data rates. See the referenced article supra.
Various circuit design methods have been used to improve the MTBF of the flip-flop. Such methods include reducing the load at the master transmission gate, or using different types of transmission gates. The improvement gained in the MTBF by using these methods is insignificant. Another method uses two clock cycles, which exacts a time penalty that is disadvantageous for high-speed systems.
A need exists for a flip-flop circuit that reduces the effect of metastability while increasing the MTBF. The present invention meets this need.